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| a FEATURES Low Noise: 0.2 V p-p 0.1 Hz to 10 Hz Low Gain TC: 5 ppm max (G = 1) Low Nonlinearity: 0.001% max (G = 1 to 200) High CMRR: 130 dB min (G = 500 to 1000) Low Input Offset Voltage: 25 V, max Low Input Offset Voltage Drift: 0.25 V/ C max Gain Bandwidth Product: 25 MHz Pin Programmable Gains of 1, 100, 200, 500, 1000 No External Components Required Internally Compensated -INPUT G = 100 G = 200 Precision Instrumentation Amplifier AD624 FUNCTIONAL BLOCK DIAGRAM 50 225.3 4445.7 124 G = 500 80.2 RG1 RG2 VB 20k 20k 10k 10k AD624 10k SENSE OUTPUT 10k 50 +INPUT REF PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD624 is a high precision, low noise, instrumentation amplifier designed primarily for use with low level transducers, including load cells, strain gauges and pressure transducers. An outstanding combination of low noise, high gain accuracy, low gain temperature coefficient and high linearity make the AD624 ideal for use in high resolution data acquisition systems. The AD624C has an input offset voltage drift of less than 0.25 V/C, output offset voltage drift of less than 10 V/C, CMRR above 80 dB at unity gain (130 dB at G = 500) and a maximum nonlinearity of 0.001% at G = 1. In addition to these outstanding dc specifications, the AD624 exhibits superior ac performance as well. A 25 MHz gain bandwidth product, 5 V/s slew rate and 15 s settling time permit the use of the AD624 in high speed data acquisition applications. The AD624 does not need any external components for pretrimmed gains of 1, 100, 200, 500 and 1000. Additional gains such as 250 and 333 can be programmed within one percent accuracy with external jumpers. A single external resistor can also be used to set the 624's gain to any value in the range of 1 to 10,000. 1. The AD624 offers outstanding noise performance. Input noise is typically less than 4 nV/Hz at 1 kHz. 2. The AD624 is a functionally complete instrumentation amplifier. Pin programmable gains of 1, 100, 200, 500 and 1000 are provided on the chip. Other gains are achieved through the use of a single external resistor. 3. The offset voltage, offset voltage drift, gain accuracy and gain temperature coefficients are guaranteed for all pretrimmed gains. 4. The AD624 provides totally independent input and output offset nulling terminals for high precision applications. This minimizes the effect of offset voltage in gain ranging applications. 5. A sense terminal is provided to enable the user to minimize the errors induced through long leads. A reference terminal is also provided to permit level shifting at the output. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999 AD624-SPECIFICATIONS (@ V = S 15 V, RL = 2 k AD624B Typ and TA = +25 C, unless otherwise noted) Min AD624C Typ Max Min AD624S Typ Max Units Model Min GAIN Gain Equation (External Resistor Gain Programming) AD624A Typ Max Min Max 40, 000 R G 1 to 1000 + 1 20% 40, 000 R G 1 to 1000 + 1 20% 40, 000 R G 1 to 1000 + 1 20% 40, 000 R G 1 to 1000 + 1 20% Gain Range (Pin Programmable) Gain Error G=1 G = 100 G = 200, 500 Nonlinearity G=1 G = 100, 200 G = 500 Gain vs. Temperature G=1 G = 100, 200 G = 500 0.05 0.25 0.5 0.005 0.005 0.005 5 10 25 200 2 5 50 75 105 110 0.03 0.15 0.35 0.003 0.003 0.005 5 10 15 75 0.5 3 25 80 110 115 0.02 0.1 0.25 0.001 0.001 0.005 5 10 15 25 0.25 2 10 75 105 110 0.05 0.25 0.5 0.005 0.005 0.005 5 10 15 75 2.0 3 50 % % % % % % ppm/C ppm/C ppm/C V V/C mV V/C dB dB dB VOLTAGE OFFSET (May be Nulled) Input Offset Voltage vs. Temperature Output Offset Voltage vs. Temperature OUT Offset Referred to the Input vs. Supply G=1 70 G = 100, 200 95 G = 500 100 INPUT CURRENT Input Bias Current vs. Temperature Input Offset Current vs. Temperature INPUT Input Impedance Differential Resistance Differential Capacitance Common-Mode Resistance Common-Mode Capacitance Input Voltage Range1 Max Differ. Input Linear (VDL) Max Common-Mode Linear (V CM) Common-Mode Rejection dc to 60 Hz with 1 k Source Imbalance G=1 G = 100, 200 G = 500 OUTPUT RATING V , RL = 2 k DYNAMIC RESPONSE Small Signal -3 dB G=1 G = 100 G = 200 G = 500 G = 1000 Slew Rate Settling Time to 0.01%, 20 V Step G = 1 to 200 G = 500 G = 1000 NOISE Voltage Noise, 1 kHz R.T.I. R.T.O. R.T.I., 0.1 Hz to 10 Hz G=1 G = 100 G = 200, 500, 1000 Current Noise 0.1 Hz to 10 Hz SENSE INPUT RIN IIN Voltage Range Gain to Output 8 10 50 20 50 35 50 20 25 15 50 20 15 10 50 20 50 35 nA pA/C nA pA/C 109 10 109 10 10 12 V - 109 10 109 10 109 10 109 10 109 10 109 10 pF pF G 2 x VD 10 12 V - G 2 x VD 10 12 V - G 2 x VD 10 12 V - G 2 x VD V V 70 100 110 10 75 105 120 10 80 110 130 10 70 100 110 10 dB dB dB V 1 150 100 50 25 5.0 15 35 75 1 150 100 50 25 5.0 15 35 75 1 150 100 50 25 5.0 15 35 75 1 150 100 50 25 5.0 15 35 75 MHz kHz kHz kHz kHz V/s s s s 4 75 10 0.3 0.2 60 10 30 1 12 8 10 4 75 10 0.3 0.2 60 10 30 1 12 8 10 4 75 10 0.3 0.2 60 10 30 1 12 8 10 4 75 10 0.3 0.2 60 10 30 1 12 nV/Hz nV/Hz V p-p V p-p V p-p pA p-p k A V % -2- REV. C AD624 Model Min REFERENCE INPUT RIN IIN Voltage Range Gain to Output 16 10 AD624A Typ 20 30 1 Max 24 Min 16 10 AD624B Typ 20 30 1 Max 24 Min 16 10 AD624C Typ 20 30 1 Max 24 Min 16 10 AD624S Typ 20 30 1 Max 24 Units k A V % TEMPERATURE RANGE Specified Performance Storage POWER SUPPLY Power Supply Range Quiescent Current 1 -25 -65 6 15 3.5 +85 +150 18 5 -25 -65 6 15 3.5 +85 +150 18 5 -25 -65 6 15 3.5 +85 +150 18 5 -55 -65 6 15 3.5 +125 +150 18 5 C C V mA NOTES VDL is the maximum differential input voltage at G = 1 for specified nonlinearity, V DL at other gains = 10 V/G. V D = actual differential input voltage. 1 Example: G = 10, V D = 0.50. VCM = 12 V - (10/2 x 0.50 V) = 9.5 V. Specifications subject to change without notice. Specifications shown in boldface are tested on all production unit at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 420 mW Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VS Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Operating Temperature Range AD624A/B/C . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C AD624S . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Lead Temperature (Soldering, 60 secs) . . . . . . . . . . . . +300C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS* CONNECTION DIAGRAM -INPUT +INPUT RG2 INPUT NULL INPUT NULL REF -VS +VS 1 2 3 4 5 6 7 8 16 RG1 15 OUTPUT NULL 14 OUTPUT NULL 13 G = 100 TOP VIEW (Not to Scale) 12 G = 200 11 G = 500 10 SENSE 9 OUTPUT AD624 SHORT TO RG2 FOR DESIRED GAIN FOR GAINS OF 1000 SHORT RG1 TO PIN 12 AND PINS 11 AND 13 TO RG2 METALIZATION PHOTOGRAPH ORDERING GUIDE Model AD624AD AD624BD AD624CD AD624SD AD624SD/883B* AD624AChips AD624SChips Temperature Range -25C to +85C -25C to +85C -25C to +85C -55C to +125C -55C to +125C -25C to +85C -25C to +85C Package Description 16-Lead Ceramic DIP 16-Lead Ceramic DIP 16-Lead Ceramic DIP 16-Lead Ceramic DIP 16-Lead Ceramic DIP Die Die Package Option D-16 D-16 D-16 D-16 D-16 Contact factory for latest dimensions Dimensions shown in inches and (mm). *See Analog Devices' military data sheet for 883B specifications. REV. C -3- AD624-Typical Characteristics 20 V 20 30 OUTPUT VOLTAGE SWING - V p-p V OUTPUT VOLTAGE SWING - INPUT VOLTAGE RANGE - 15 +25 C 10 15 20 10 10 5 5 0 0 5 15 10 SUPPLY VOLTAGE - V 20 0 0 10 5 15 SUPPLY VOLTAGE - V 20 0 10 100 1k LOAD RESISTANCE - 10k Figure 1. Input Voltage Range vs. Supply Voltage, G = 1 Figure 2. Output Voltage Swing vs. Supply Voltage Figure 3. Output Voltage Swing vs. Load Resistance 8.0 AMPLIFIER QUIESCENT CURRENT - mA 16 14 40 30 INPUT BIAS CURRENT - nA nA INPUT BIAS CURRENT - 6.0 12 10 8 6 4 2 20 10 0 -10 -20 -30 -40 -125 4.0 2.0 0 0 5 10 15 SUPPLY VOLTAGE - V 20 0 0 10 5 15 SUPPLY VOLTAGE - V 20 -75 -25 25 75 TEMPERATURE - C 125 Figure 4. Quiescent Current vs. Supply Voltage Figure 5. Input Bias Current vs. Supply Voltage Figure 6. Input Bias Current vs. Temperature 16 14 12 -1 VOS FROM FINAL VALUE - V nA 0 1 2 3 4 1 GAIN - V/V 500 100 10 INPUT BIAS CURRENT - 10 8 6 4 2 0 5 6 0 10 5 INPUT VOLTAGE - 15 V 20 7 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 WARM-UP TIME - Minutes 8.0 0 1 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 7. Input Bias Current vs. CMV Figure 8. Offset Voltage, RTI, Turn On Drift Figure 9. Gain vs. Frequency -4- REV. C AD624 -140 -120 -100 CMRR - dB G = 500 FULL-POWER RESPONSE - V p-p 30 160 POWER SUPPLY REJECTION - dB 140 120 100 80 60 40 20 0 10 G = 100 G = 500 -VS = -15V dc+ 1V p-p SINEWAVE G=1 -80 -60 -40 -20 0 1 20 G = 500 G = 1, 100 G = 100 10 G = 1000 G = 100 - G=1 BANDWIDTH LIMITED 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M 0 1k 10k 100k FREQUENCY - Hz 1M 100 1k 10k FREQUENCY - Hz 100k Figure 10. CMRR vs. Frequency RTI, Zero to 1k Source Imbalance Figure 11. Large Signal Frequency Response Figure 12. Positive PSRR vs. Frequency 160 CURRENT NOISE SPECTRAL DENSITY - fA/ Hz 1000 -VS = -15V dc+ 1V p-p SINEWAVE VOLT NSD - nV/ Hz 100k POWER SUPPLY REJECTION - dB 140 120 100 80 G = 500 100 G=1 G = 10 10k 10 G = 100, 1000 G = 1000 1 1000 G = 100 60 40 G=1 20 0 10 100 0.1 100 1k 10k FREQUENCY - Hz 100k 1 10 100 1k 10k FREQUENCY - Hz 100k 10 0.1 1 10 100 10k FREQUENCY - Hz 100k Figure 13. Negative PSRR vs. Frequency Figure 14. RTI Noise Spectral Density vs. Gain Figure 15. Input Current Noise -12 TO 12 -8 TO 8 -4 TO 4 OUTPUT STEP -V 4 TO -4 8 TO -8 1% 0.1% 0.01% 1% 12 TO -12 0.1% 0.01% 0 5 10 15 SETTLING TIME - s 20 Figure 16. Low Frequency Voltage Noise, G = 1 (System Gain = 1000) Figure 17. Low Frequency Voltage Noise, G = 1000 (System Gain = 100,000) Figure 18. Settling Time, Gain = 1 REV. C -5- AD624 -12 TO 12 -8 TO 8 -4 TO 4 OUTPUT STEP -V 4 TO -4 8 TO -8 1% 12 TO -12 0.1% 0.01% 1% 0.1% 0.01% 0 5 10 15 SETTLING TIME - s 20 Figure 19. Large Signal Pulse Response and Settling Time, G = 1 Figure 20. Settling Time Gain = 100 Figure 21. Large Signal Pulse Response and Settling Time, G = 100 -12 TO 12 -8 TO 8 -4 TO 4 OUTPUT STEP -V 4 TO -4 8 TO -8 12 TO -12 0 5 1% 0.1% 0.01% 1% 0.1% 0.01% 10 15 SETTLING TIME - s 20 Figure 22. Range Signal Pulse Response and Settling Time, G = 500 Figure 23. Settling Time Gain = 1000 Figure 24. Large Signal Pulse Response and Settling Time, G = 1000 -6- REV. C AD624 10k 1% INPUT 20V p-p +VS 1k 10T 10k 1% VOUT 100k 1% RG1 G = 100 G = 200 1k 0.1% 500 0.1% 200 0.1% G = 500 RG2 AD624 -VS Figure 25. Settling Time Test Circuit THEORY OF OPERATION The AD624 is a monolithic instrumentation amplifier based on a modification of the classic three-op-amp instrumentation amplifier. Monolithic construction and laser-wafer-trimming allow the tight matching and tracking of circuit components and the high level of performance that this circuit architecture is capable of. A preamp section (Q1-Q4) develops the programmed gain by the use of feedback concepts. Feedback from the outputs of A1 and A2 forces the collector currents of Q1-Q4 to be constant thereby impressing the input voltage across RG. The gain is set by choosing the value of RG from the equation, 40 k + 1. The value of RG also sets the transconductGain = RG ance of the input preamp stage increasing it asymptotically to the transconductance of the input transistors as RG is reduced for larger gains. This has three important advantages. First, this approach allows the circuit to achieve a very high open loop gain of 3 x 108 at a programmed gain of 1000 thus reducing gain related errors to a negligible 3 ppm. Second, the gain bandwidth product which is determined by C3 or C4 and the input transconductance, reaches 25 MHz. Third, the input voltage noise reduces to a value determined by the collector current of the input transistors for an RTI noise of 4 nV/Hz at G 500. +VS +VS 16.2k The AD524 should be considered in applications that require protection from severe input overload. If this is not possible, external protection resistors can be put in series with the inputs of the AD624 to augment the internal (50 ) protection resistors. This will most seriously degrade the noise performance. For this reason the value of these resistors should be chosen to be as low as possible and still provide 10 mA of current limiting under maximum continuous overload conditions. In selecting the value of these resistors, the internal gain setting resistor and the 1.2 volt drop need to be considered. For example, to protect the device from a continuous differential overload of 20 V at a gain of 100, 1.9 k of resistance is required. The internal gain resistor is 404 ; the internal protect resistor is 100 . There is a 1.2 V drop across D1 or D2 and the base-emitter junction of either Q1 and Q3 or Q2 and Q4 as shown in Figure 27, 1400 of external resistance would be required (700 in series with each input). The RTI noise in this case would be 4 KTRext +(4 nV / Hz )2 = 6.2 nV / Hz +VS I1 50 A A1 VB I2 50 A R52 10k SENSE C3 A2 C4 R53 10k A3 RG2 500 124 4445 200 225.3 100 -VS R56 20k Q2, Q4 R54 10k VO 50 100 200 500 RG2 1F G500 -VS Q1, Q3 R57 20k RG1 -IN 1F 1/2 AD712 16.2k -VS 1.62M 1F 1.82k AD624 1/2 AD712 9.09k G1, 100, 200 1k 100 13 50 A 80.2 I4 50 A 50 R55 10k REF +IN Figure 26. Noise Test Circuit Figure 27. Simplified Circuit of Amplifier; Gain Is Defined as (R56 + R57)/(RG) + 1. For a Gain of 1, RG Is an Open Circuit. INPUT OFFSET AND OUTPUT OFFSET Under input overload conditions the user will see RG + 100 and two diode drops (~1.2 V) between the plus and minus inputs, in either direction. If safe overload current under all conditions is assumed to be 10 mA, the maximum overload voltage is ~ 2.5 V. While the AD624 can withstand this continuously, momentary overloads of 10 V will not harm the device. On the other hand the inputs should never exceed the supply voltage. REV. C -7- INPUT CONSIDERATIONS Voltage offset specifications are often considered a figure of merit for instrumentation amplifiers. While initial offset may be adjusted to zero, shifts in offset voltage due to temperature variations will cause errors. Intelligent systems can often correct for this factor with an autozero cycle, but there are many smallsignal high-gain applications that don't have this capability. Voltage offset and offset drift each have two components; input and output. Input offset is that component of offset that is AD624 directly proportional to gain i.e., input offset as measured at the output at G = 100 is 100 times greater than at G = 1. Output offset is independent of gain. At low gains, output offset drift is dominant, while at high gains input offset drift dominates. Therefore, the output offset voltage drift is normally specified as drift at G = 1 (where input effects are insignificant), while input offset voltage drift is given by drift specification at a high gain (where output offset effects are negligible). All inputrelated numbers are referred to the input (RTI) which is to say that the effect on the output is "G" times larger. Voltage offset vs. power supply is also specified at one or more gain settings and is also RTI. By separating these errors, one can evaluate the total error independent of the gain setting used. In a given gain configuration both errors can be combined to give a total error referred to the input (R.T.I.) or output (R.T.O.) by the following formula: Total Error R.T.I. = input error + (output error/gain) Total Error R.T.O. = (Gain x input error) + output error As an illustration, a typical AD624 might have a +250 V output offset and a -50 V input offset. In a unity gain configuration, the total output offset would be 200 V or the sum of the two. At a gain of 100, the output offset would be -4.75 mV or: +250 V + 100 (-50 V) = -4.75 mV. The AD624 provides for both input and output offset adjustment. This optimizes nulling in very high precision applications and minimizes offset voltage effects in switched gain applications. In such applications the input offset is adjusted first at the highest programmed gain, then the output offset is adjusted at G = 1. GAIN Table I. Gain (Nominal) 1 100 125 137 186.5 200 250 333 375 500 624 688 831 1000 Temperature Coefficient (Nominal) -0 ppm/C -1.5 ppm/C -5 ppm/C -5.5 ppm/C -6.5 ppm/C -3.5 ppm/C -5.5 ppm/C -15 ppm/C -0.5 ppm/C -10 ppm/C -5 ppm/C -1.5 ppm/C +4 ppm/C 0 ppm/C Pin 3 to Pin - 13 13 13 13 12 12 12 12 11 11 11 11 11 Connect Pins - - 11 to 16 11 to 12 11 to 12 to 16 - 11 to 13 11 to 16 13 to 16 - 13 to 16 11 to 12; 13 to 16 16 to 12 16 to 12; 13 to 11 Pins 3 and 16 programs the gain according to the formula 40k RG = G -1 (see Figure 29). For best results RG should be a precision resistor with a low temperature coefficient. An external RG affects both gain accuracy and gain drift due to the mismatch between it and the internal thin-film resistors R56 and R57. Gain accuracy is determined by the tolerance of the external RG and the absolute accuracy of the internal resistors (20%). Gain drift is determined by the mismatch of the temperature coefficient of RG and the temperature coefficient of the internal resistors (-15 ppm/C typ), and the temperature coefficient of the internal interconnections. +VS -INPUT RG1 1.5k 1k OR 2.105k RG2 +INPUT -VS The AD624 includes high accuracy pretrimmed internal gain resistors. These allow for single connection programming of gains of 1, 100, 200 and 500. Additionally, a variety of gains including a pretrimmed gain of 1000 can be achieved through series and parallel combinations of the internal resistors. Table I shows the available gains and the appropriate pin connections and gain temperature coefficients. The gain values achieved via the combination of internal resistors are extremely useful. The temperature coefficient of the gain is dependent primarily on the mismatch of the temperature coefficients of the various internal resistors. Tracking of these resistors is extremely tight resulting in the low gain TCs shown in Table I. If the desired value of gain is not attainable using the internal resistors, a single external resistor can be used to achieve any gain between 1 and 10,000. This resistor connected between +VS -INPUT RG1 G = 100 G = 200 G = 500 RG2 +INPUT -VS 10k INPUT OFFSET NULL AD624 VOUT REFERENCE G = 40.000 + 1 = 20 2.105 20% Figure 29. Operating Connections for G = 20 The AD624 may also be configured to provide gain in the output stage. Figure 30 shows an H pad attenuator connected to the reference and sense lines of the AD624. The values of R1, R2 and R3 should be selected to be as low as possible to minimize the gain variation and reduction of CMRR. Varying R2 will precisely set the gain without affecting CMRR. CMRR is determined by the match of R1 and R3. +VS -INPUT RG1 G = 100 G = 200 G = 500 RG2 +INPUT -VS G= (R2||20k ) + R1 + R3) (R2||20k ) (R1 + R2 + R3) || RL 2k R3 6k R1 6k R2 5k AD624 OUTPUT SIGNAL COMMON VOUT AD624 RL VOUT Figure 28. Operating Connections for G = 200 Figure 30. Gain of 2500 -8- REV. C AD624 NOISE +VS The AD624 is designed to provide noise performance near the theoretical noise floor. This is an extremely important design criteria as the front end noise of an instrumentation amplifier is the ultimate limitation on the resolution of the data acquisition system it is being used in. There are two sources of noise in an instrument amplifier, the input noise, predominantly generated by the differential input stage, and the output noise, generated by the output amplifier. Both of these components are present at the input (and output) of the instrumentation amplifier. At the input, the input noise will appear unaltered; the output noise will be attenuated by the closed loop gain (at the output, the output noise will be unaltered; the input noise will be amplified by the closed loop gain). Those two noise sources must be root sum squared to determine the total noise level expected at the input (or output). The low frequency (0.1 Hz to 10 Hz) voltage noise due to the output stage is 10 V p-p, the contribution of the input stage is 0.2 V p-p. At a gain of 10, the RTI voltage noise would be 1 V p-p, 2 10 + (0.2) . The RTO voltage noise would be G 2 AD624 LOAD -VS TO POWER SUPPLY GROUND c. AC-Coupled Figure 31. Indirect Ground Returns for Bias Currents Although instrumentation amplifiers have differential inputs, there must be a return path for the bias currents. If this is not provided, those currents will charge stray capacitances, causing the output to drift uncontrollably or to saturate. Therefore, when amplifying "floating" input sources such as transformers and thermocouples, as well as ac-coupled sources, there must still be a dc path from each input to ground, (see Figure 31). COMMON-MODE REJECTION 10.2 V p-p, 102 + 0.2(G ) ( ) 2 . These calculations hold for applications using either internal or external gain resistors. INPUT BIAS CURRENTS Input bias currents are those currents necessary to bias the input transistors of a dc amplifier. Bias currents are an additional source of input error and must be considered in a total error budget. The bias currents when multiplied by the source resistance imbalance appear as an additional offset voltage. (What is of concern in calculating bias current errors is the change in bias current with respect to signal voltage and temperature.) Input offset current is the difference between the two input bias currents. The effect of offset current is an input offset voltage whose magnitude is the offset current times the source resistance. +VS Common-mode rejection is a measure of the change in output voltage when both inputs are changed by equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. "Common-Mode Rejection Ratio" (CMRR) is a ratio expression while "CommonMode Rejection" (CMR) is the logarithm of that ratio. For example, a CMRR of 10,000 corresponds to a CMR of 80 dB. In an instrumentation amplifier, ac common-mode rejection is only as good as the differential phase shift. Degradation of ac common-mode rejection is caused by unequal drops across differing track resistances and a differential phase shift due to varied stray capacitances or cable capacitances. In many applications shielded cables are used to minimize noise. This technique can create common-mode rejection errors unless the shield is properly driven. Figures 32 and 33 shows active data guards which are configured to improve ac common-mode rejection by "bootstrapping" the capacitances of the input cabling, thus minimizing differential phase shift. +VS -INPUT AD624 LOAD G = 200 100 RG2 AD624 VOUT -VS TO POWER SUPPLY GROUND AD711 REFERENCE +INPUT -VS a. Transformer Coupled +VS Figure 32. Shield Driver, G 100 +VS -INPUT 100 AD712 RG1 AD624 AD624 LOAD 100 -VS RG2 VOUT -VS TO POWER SUPPLY GROUND +INPUT -VS REFERENCE Figure 33. Differential Shield Driver b. Thermocouple REV. C -9- AD624 GROUNDING Many data-acquisition components have two or more ground pins which are not connected together within the device. These grounds must be tied together at one point, usually at the system power supply ground. Ideally, a single solid ground would be desirable. However, since current flows through the ground wires and etch stripes of the circuit cards, and since these paths have resistance and inductance, hundreds of millivolts can be generated between the system ground point and the data acquisition components. Separate ground returns should be provided to minimize the current flow in the path from the most sensitive points to the system ground point. In this way supply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors (see Figure 34). ANALOG P.S. +15V C -15V DIGITAL P.S. C +5V "inside the loop" of an instrumentation amplifier to provide the required current without significantly degrading overall performance. The effects of nonlinearities, offset and gain inaccuracies of the buffer are reduced by the loop gain of the IA output amplifier. Offset drift of the buffer is similarly reduced. REFERENCE TERMINAL The reference terminal may be used to offset the output by up to 10 V. This is useful when the load is "floating" or does not share a ground with the rest of the system. It also provides a direct means of injecting a precise offset. It must be remembered that the total output swing is 10 volts, from ground, to be shared between signal and reference offset. +VS SENSE VIN+ AD624 REF LOAD VIN- 0.1 0.1 F F 0.1 0.1 F F DIG COM 1F1F 1F -VS + AD574A SIGNAL GROUND DIGITAL DATA OUTPUT AD711 VOFFSET AD624 ANALOG GROUND* AD583 SAMPLE AND HOLD Figure 36. Use of Reference Terminal to Provide Output Offset OUTPUT REFERENCE *IF INDEPENDENT, OTHERWISE RETURN AMPLIFIER REFERENCE TO MECCA AT ANALOG P.S. COMMON Figure 34. Basic Grounding Practice Since the output voltage is developed with respect to the potential on the reference terminal an instrumentation amplifier can solve many grounding problems. SENSE TERMINAL When the IA is of the three-amplifier configuration it is necessary that nearly zero impedance be presented to the reference terminal. Any significant resistance, including those caused by PC layouts or other connection techniques, which appears between the reference pin and ground will increase the gain of the noninverting signal path, thereby upsetting the commonmode rejection of the IA. Inadvertent thermocouple connections created in the sense and reference lines should also be avoided as they will directly affect the output offset voltage and output offset voltage drift. In the AD624 a reference source resistance will unbalance the CMR trim by the ratio of 10 k/RREF. For example, if the reference source impedance is 1 , CMR will be reduced to 80 dB (10 k/1 = 80 dB). An operational amplifier may be used to provide that low impedance reference point as shown in Figure 36. The input offset voltage characteristics of that amplifier will add directly to the output offset voltage performance of the instrumentation amplifier. An instrumentation amplifier can be turned into a voltage-tocurrent converter by taking advantage of the sense and reference terminals as shown in Figure 37. SENSE +INPUT The sense terminal is the feedback point for the instrument amplifier's output amplifier. Normally it is connected to the instrument amplifier output. If heavy load currents are to be drawn through long leads, voltage drops due to current flowing through lead resistance can cause errors. The sense terminal can be wired to the instrument amplifier at the load thus putting the IxR drops "inside the loop" and virtually eliminating this error source. V+ (SENSE) OUTPUT CURRENT BOOSTER VIN+ AD624 VIN- X1 RL (REF) R1 +VX- AD624 -INPUT IL V- AD711 REF A2 LOAD Figure 35. AD624 Instrumentation Amplifier with Output Current Booster Typically, IC instrumentation amplifiers are rated for a full 10 volt output swing into 2 k. In some applications, however, the need exists to drive more current into heavier loads. Figure 35 shows how a current booster may be connected IL = VIN VX 40.000 1+ = R1 R1 RG Figure 37. Voltage-to-Current Converter -10- REV. C AD624 -IN +IN 50 1 16 50 2 3 80.2 4445.7 20k VB 10k 20k 10k 10k 15 14 13 OUTPUT OFFSET TRIM R2 10k G = 100 K1 NC G = 200 K2 G = 500 K3 INPUT OFFSET TRIM R1 10k 4 5 225.3 12 RELAY SHIELDS 10k 6 124 11 +5V 10 9 -VS +VS 1F 35V ANALOG COMMON 7 K1 OUT D1 K2 D2 K3 D3 AD624 8 C1 C2 K1 - K3 = THERMOSEN DM2C 4.5V COIL D1 - D3 = IN4148 INPUTS A GAIN RANGE B 74LS138 DECODER Y0 Y1 Y2 7407N BUFFER DRIVER 10 F GAIN TABLE AB GAIN 00 100 01 500 10 200 11 1 +5V LOGIC COMMON Figure 38. Gain Programmable Amplifier By establishing a reference at the "low" side of a current setting resistor, an output current may be defined as a function of input voltage, gain and the value of that resistor. Since only a small current is demanded at the input of the buffer amplifier A2, the forced current IL will largely flow through the load. Offset and drift specifications of A2 must be added to the output offset and drift specifications of the IA. PROGRAMMABLE GAIN symmetrical bipolar transmission is ideal in this application. The multiplying DAC's advantage is that it can handle inputs of either polarity or zero without affecting the programmed gain. The circuit shown uses an AD7528 to set the gain (DAC A) and to perform a fine adjustment (DAC B). -IN (+INPUT) 1 50 16 Figure 38 shows the AD624 being used as a software programmable gain amplifier. Gain switching can be accomplished with mechanical switches such as DIP switches or reed relays. It should be noted that the "on" resistance of the switch in series with the internal gain resistor becomes part of the gain equation and will have an effect on gain accuracy. A significant advantage in using the internal gain resistors in a programmable gain configuration is the minimization of thermocouple signals which are often present in multiplexed data acquisition systems. If the full performance of the AD624 is to be achieved, the user must be extremely careful in designing and laying out his circuit to minimize the remaining thermocouple signals. The AD624 can also be connected for gain in the output stage. Figure 39 shows an AD547 used as an active attenuator in the output amplifier's feedback loop. The active attenuation presents a very low impedance to the feedback resistors therefore minimizing the common-mode rejection ratio degradation. Another method for developing the switching scheme is to use a DAC. The AD7528 dual DAC which acts essentially as a pair of switched resistive attenuators having high analog linearity and +IN (-INPUT) 50 2 3 80.2 4445.7 15 14 13 OUTPUT OFFSET NULL TO -V 10k INPUT OFFSET NULL 10k 4 5 20k 10k VB 20k 10k 10k 225.3 12 124 11 10 9 6 10k -VS +VS 1F 35V 7 AD624 8 VOUT 10pF +VS VSS VDD GND 39.2k 1k 1k 1k AD711 -VS 28.7k 316k AD7590 A1 A2 A3 A4 WR Figure 39. Programmable Output Gain REV. C -11- AD624 +INPUT (-INPUT) G = 100 225.3 G = 200 124 G = 500 80.2 RG1 RG2 20k 20k 50 -VS 50 In many applications complex software algorithms for autozero applications are not available. For these applications Figure 42 provides a hardware solution. AD624 VB 10k 10k VOUT 10k 10k 15 16 14 13 RG2 RG1 +VS 4445.7 AD624 0.1 F LOW LEAKAGE 1k 9 10 VOUT CH -INPUT (+INPUT) AD542 12 11 +VS 1/2 AD712 DAC A DATA INPUTS CS WR DAC A/DAC B DAC B DB0 DB7 256:1 VDD VSS GND A1 200 s A2 A3 A4 AD7510DIKD AD7528 1/2 AD712 ZERO PULSE Figure 42. Autozero Circuit Figure 40. Programmable Output Gain Using a DAC AUTOZERO CIRCUITS In many applications it is necessary to provide very accurate data in high gain configurations. At room temperature the offset effects can be nulled by the use of offset trimpots. Over the operating temperature range, however, offset nulling becomes a problem. The circuit of Figure 41 shows a CMOS DAC operating in the bipolar mode and connected to the reference terminal to provide software controllable offset adjustments. +VS -INPUT RG1 G = 100 G = 200 G = 500 RG2 +INPUT -VS 39k -VS +VS RFB OUT1 C1 +VS R4 10k VREF R3 20k The microprocessor controlled data acquisition system shown in Figure 43 includes includes both autozero and autogain capability. By dedicating two of the differential inputs, one to ground and one to the A/D reference, the proper program calibration cycles can eliminate both initial accuracy errors and accuracy errors over temperature. The autozero cycle, in this application, converts a number that appears to be ground and then writes that same number (8 bit) to the AD624 which eliminates the zero error since its output has an inverted scale. The autogain cycle converts the A/D reference and compares it with full scale. A multiplicative correction factor is then computed and applied to subsequent readings. RG2 VREF AD624 AD583 VOUT AD7507 AD624 VIN AD574A AGND RG1 A0 A2 EN A1 20k R5 20k -VREF 20k AD589 MSB DATA INPUTS CS WR LSB 1/2 AD712 LATCH AD7524 10k AD7524 OUT2 1/2 AD712 5k 1/2 AD712 DECODE CONTROL 1/2 AD712 R6 5k -VS GND Figure 41. Software Controllable Offset ADDRESS BUS MICROPROCESSOR Figure 43. Microprocessor Controlled Data Acquisition System -12- REV. C AD624 WEIGH SCALE Figure 44 shows an example of how an AD624 can be used to condition the differential output voltage from a load cell. The 10% reference voltage adjustment range is required to accommodate the 10% transducer sensitivity tolerance. The high linearity and low noise of the AD624 make it ideal for use in applications of this type particularly where it is desirable to measure small changes in weight as opposed to the absolute value. The addition of an autogain/autotare cycle will enable the system to remove offsets, gain errors, and drifts making possible true 14-bit performance. +15V NOTE 2 10V 10% 100 +5V R1 30k R2 20k R3 10k SCALE ERROR ADJUST +15V +10V R3 10 Figure 45 is an example of an ac bridge system with the AD630 used as a synchronous demodulator. The oscilloscope photograph shows the results of a 0.05% bridge imbalance caused by the 1 Meg resistor in parallel with one leg of the bridge. The top trace represents the bridge excitation, the upper middle trace is the amplified bridge output, the lower-middle trace is the output of the synchronous demodulator and the bottom trace is the filtered dc system output. This system can easily resolve a 0.5 ppm change in bridge impedance. Such a change will produce a 6.3 mV change in the low-pass filtered dc output, well above the RTO drifts and noise. The AC-CMRR of the AD624 decreases with the frequency of the input signal. This is due mainly to the package-pin capacitance associated with the AD624's internal gain resistors. If AC-CMRR is not sufficient for a given application, it can be trimmed by using a variable capacitor connected to the amplifier's RG2 pin as shown in Figure 45. 1kHz BRIDGE EXCITATION +VS 10k 1k 1k 1k 1M RG1 AD707 2N2219 AD584 +2.5V VBG -INPUT G500 G200 G100 R5 3M R4 10k ZERO ADJUST (FINE) RG2 +INPUT R7 100k R6 100k ZERO ADJUST (COARSE) NOTES 1. LOAD CELL TEDEA MODEL 1010 10kG. OUTPUT 2mV/V 10%. 2. R1, R2 AND R3 SELECTED FOR AD584. OUTPUT 10V 10%. GAIN = 500 TRANSDUCER SEE NOTE 1 SENSE +10V FULL SCALE OUTPUT A/D CONVERTER 1k G = 1000 RG2 4-49pF CERAMIC ac BALANCE CAPACITOR AD624C AD624 OUT REFERENCE -VS 2.5k PHASE SHIFTER MODULATION INPUT A B 2.5k B 5k Figure 44. AD624 Weigh Scale Application AC BRIDGE 10k 10k -VS CARRIER INPUT -V MODULATED OUTPUT SIGNAL VOUT Bridge circuits which use dc excitation are often plagued by errors caused by thermocouple effects, l/f noise, dc drifts in the electronics, and line noise pickup. One way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. The ac phase and amplitude information from the bridge is recovered as a dc signal at the output of the synchronous demodulator. The low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a lowpass filter. Dynamic response of the bridge must be traded off against the amount of attenuation required to adequately suppress these residual carrier components in the selection of the filter. COMP AD630 +VS Figure 45. AC Bridge 0V 0V 0V BRIDGE EXCITATION (20V/div) (A) AMPLIFIED BRIDGE OUTPUT (5V/div) (B) DEMODULATED BRIDGE OUTPUT (5V/div) (C) 0V 2V FILTER OUTPUT 2V/div) (D) Figure 46. AC Bridge Waveforms REV. C -13- AD624 ERROR BUDGET ANALYSIS +VS +10V RG1 350 350 G = 100 350 350 RG2 -VS To illustrate how instrumentation amplifier specifications are applied, we will now examine a typical case where an AD624 is required to amplify the output of an unbalanced transducer. Figure 47 shows a differential transducer, unbalanced by 5 , supplying a 0 to 20 mV signal to an AD624C. The output of the IA feeds a 14-bit A to D converter with a 0 to 2 volt input voltage range. The operating temperature range is -25C to +85C. Therefore, the largest change in temperature T within the operating range is from ambient to +85C (85C - 25C = 60C.) In many applications, differential linearity and resolution are of prime importance. This would be so in cases where the absolute value of a variable is less important than changes in value. In these applications, only the irreducible errors (20 ppm = 0.002%) are significant. Furthermore, if a system has an intelligent processor monitoring the A to D output, the addition of an autogain/autozero cycle will remove all reducible errors and may eliminate the requirement for initial calibration. This will also reduce errors to 0.002%. 10k AD624C 14-BIT ADC 0 TO 2V F.S. Figure 47. Typical Bridge Application Table II. Error Budget Analysis of AD624CD in Bridge Application Error Source Gain Error Gain Instability Gain Nonlinearity Input Offset Voltage Input Offset Voltage Drift Output Offset Voltage1 Output Offset Voltage Drift1 Bias Current-Source Imbalance Error Offset Current-Source Imbalance Error Offset Current-Source Resistance Error Offset Current-Source Resistance-Drift Common-Mode Rejection 5 V dc Noise, RTI (0.1 Hz-10 Hz) AD624C Specifications 0.1% 10 ppm 0.001% 25 V, RTI 0.25 V/C 2.0 mV 10 V/C 15 nA 10 nA 10 nA 100 pA/C 115 dB 0.22 V p-p Calculation 0.1% = 1000 ppm (10 ppm/C) (60C) = 600 ppm 0.001% = 10 ppm 25 V/20 mV = 1250 ppm ( 0.25 V/C) (60C)= 15 V 15 V/20 mV = 750 ppm 2.0 mV/20 mV = 1000 ppm ( 10 V/C) (60C) = 600 V 600 V/20 mV = 300 ppm ( 15 nA)(5 ) = 0.075 V 0.075 V/20mV = 3.75 ppm ( 10 nA)(5 ) = 0.050 V 0.050 V/20 mV = 2.5 ppm (10 nA) (175 ) = 1.75 V 1.75 V/20 mV = 87.5 ppm (100 pA/C) (175 ) (60C) = 1 V 1 V/20 mV = 50 ppm 115 dB = 1.8 ppm x 5 V = 9 V 9 V/20 mV = 444 ppm 0.22 V p-p/20 mV = 10 ppm Total Error Effect on Absolute Accuracy at TA = +25 C 1000 ppm _ - 1250 ppm - 1000 ppm - 3.75 ppm 2.5 ppm 87.5 ppm - 450 ppm _ 3793.75 ppm Effect on Absolute Effect Accuracy on at TA = +85 C Resolution 1000 ppm 600 ppm - 1250 ppm 750 ppm 1000 ppm 300 ppm 3.75 ppm 2.5 ppm 87.5 ppm 50 ppm 450 ppm - 5493.75 ppm - - 10 ppm - - - - - - - - - 10 ppm 20 ppm NOTE 1 Output offset voltage and output offset voltage drift are given as RTI figures. For a comprehensive study of instrumentation amplifier design and applications, refer to the Instrumentation Amplifier Application Guide, available free from Analog Devices. -14- REV. C AD624 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Side-Brazed Solder Lid Ceramic DIP (D-16) 0.005 (0.13) MIN 16 0.080 (2.03) MAX 9 0.310 (7.87) 0.220 (5.59) 1 8 PIN 1 0.840 (21.34) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) 0.100 (2.54) BSC 0.150 (3.81) MAX 0.070 (1.78) SEATING PLANE 0.030 (0.76) 0.015 (0.38) 0.008 (0.20) REV. C -15- PRINTED IN U.S.A. C805d-0-7/99 |
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